1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to a semiconductor memory device including a redundancy circuit for carrying out substitution between defective memory cell rows or columns and redundancy memory cell rows or columns.
2. Description of the Background Art
Conventionally, semiconductor memory devices such as static random access memories (hereinafter referred to as "SRAMs") and dynamic random access memories (hereinafter referred to as "DRAMs") incorporate redundancy circuits in order to increase production yield of the semiconductor memory devices. If any defects occur in memories incorporated in the manufactured semiconductor memory devices, the defective memories are rescued by the function of the redundancy circuits. While this invention is generally applicable to such semiconductor memory devices as SRAMs and DRAMs, a description will be given on one example in which this invention is applied to an SRAM.
FIG. 14 is a partly omitted circuit block diagram showing a configuration of a conventional SRAM. With reference to FIG. 14, this conventional SRAM includes a memory cell array 50 and a redundancy memory cell array 52. A plurality of bit line pairs BL and /BL are provided in common in memory cell array 50 and redundancy memory cell array 52. Memory cell array 50 includes a plurality (uxi) of word lines WL1-WLui intersecting bit line pairs BL and /BL, and memory cells 51 each provided at respective intersections of bit line pairs BL and /BL and word lines WL1-WLui. Word lines WL1-WLui are in groups of i. Redundancy memory cell array 52 includes a plurality (n) of spare word lines SWL1-SWLn intersecting bit line pairs BL and /BL, and redundancy memory cells 53 each provided at respective intersections of bit line pairs BL and /BL and spare word lines SWL1-SWLn.
The SRAM further includes a bit line load circuit 54 provided at one end of bit line pairs BL and /BL, a column selecting gate 55 and a read/write circuit 56 both provided at the other end of bit line pairs BL and /BL, and an input buffer 57, a column address predecoder group 58 and a column decoder group 59 for driving column selecting gate 55 in response to an external column address signal CA.
The SRAM further includes a row decoder group 60 provided at one end of word lines WL1-WLui, a redundancy row decoder group 61 provided at one end of spare word lines SWL1-SWLn, an input buffer 62 receiving an external row address signal RA, and a row address predecoder group 63 for converting the row address signal RA applied via input buffer 62 to predecode signals A1-Am to apply the signals A1-Am to row decoder group 60 and redundancy row decoder group 61. Row decoder group 60 includes a plurality (uxi) of row decoders D11-Dui each provided for their corresponding word lines WL1-WLui. Row decoders D11-Dui are set in groups of i in correspondence with word lines WL1-WLui.
Predecode signals A1-Am are divided into groups of t+1. For example, the first group includes i signals A1-Ai. Only one signal from each group is input to each of row decoders D11-Dui. For example, row decoder D11 receives a signal A1 of the first group, a signal a111 of the second group, a signal a112 of the third group, . . . and a signal a11t of the final group. When all signals A1, a111, a112, . . . and a11t attain a logic high level or an "H" level (selection level), row decoder D11 raises word line WL1 to a logic high level.
Redundancy row decoder group 61 includes a plurality (n) of redundancy row decoders SD1'-SDn' each provided for their corresponding spare word lines SWL1-SWLn.
FIG. 15 is a circuit block diagram showing a configuration of redundancy row decoder SD1'. FIG. 16 is a circuit block diagram showing a configuration of an address program circuit 70.1 of FIG. 15. FIG. 17 is a circuit diagram showing a configuration of a fuse circuit 80 of FIG. 16. An enable circuit 71 of FIG. 15 is the same as fuse circuit 80 of FIG. 17.
With reference to FIG. 17, fuse circuit 80 includes a fuse 90 connected between a power source line 101 and a node N90, a capacitor 91, a high resistance element 92 and an N channel MOS transistor 93 connected in parallel between node N90 and a ground potential line 102, and an inverter 94 connected between node N90 and a gate of an N channel MOS transistor 93. An output of inverter 94 becomes an output f of fuse circuit 80.
If fuse 90 is not cut off, capacitor 91 is charged via fuse 90, and node N90 attains a logic high level (a power supply potential Vcc). Accordingly, inverter 94 outputs a logic low level (a ground potential GND). In response to this output, N channel MOS transistor 93 is rendered nonconductive, and node N90 is held at a logic high level.
Conversely, if fuse 90 is cut off, charges of capacitor 91 are discharged via high resistance element 92, and node N90 attains a logic low level. Accordingly, inverter 94 outputs a logic high level, so that N channel MOS transistor 93 is rendered conductive and node N90 is held at a logic low level.
Address program circuit 70.1 includes a fuse circuit 80, an inverter 81 and a transfer gate 82, as shown in FIG. 16. Transfer gate 82 includes a P channel MOS transistor 83 and an N channel MOS transistor 84 with their conduction electrodes connected to each other. An output f of fuse circuit 80 is input via inverter 81 to a gate of P channel MOS transistor 83 and also directly to a gate of N channel MOS transistor 84. A predecode signal A1 is input to one conduction electrode of transfer gate 82, and a signal output from the other conduction electrode of transfer gate 82 becomes an output signal REDA1 of address program circuit 70.1.
If fuse 90 is not cut off and output f of fuse circuit 80 is at a logic low level, transfer gate 82 is rendered nonconductive so as to prevent the input of predecode signal A1. In this case, output REDA1 of address program circuit 70.1 is put in a floating state.
Conversely, if fuse 90 is cut off and output f of fuse circuit 80 is at a logic high level, transfer gate 82 is rendered conductive so as to allow predecode signal A1 to pass through the transfer gate. In this case, output REDA1 of address program circuit 70.1 is set at the same level as that of predecode signal A1. The operations of other address program circuits 70.2-70.m are similar to the foregoing operation.
Redundancy row decoder SD1' includes address program circuits 70.1-70.m, enable circuit 71, an NAND gate 72 and an inverter 73, as shown in FIG. 15. Address program circuits 70.1-70.m receive predecode signals A1-Am, respectively. Address program circuits 70.1-70.m are divided into groups of t+1 in correspondence with predecode signals A1-Am. Respective output nodes of address program circuits 70.1-70.i; . . . of each group are connected in common. NAND gate 72 receives outputs of address program circuits 70.1-70.i; . . . in groups and an output f of enable circuit 71. An output node of NAND gate 72 is connected via inverter 73 to spare word line SWL1.
When all memory cells 51 of memory cell array 50 are normal and spare word line SWL1 is not used, fuse 90 is not cut off and outputs f of enable circuit 71 and fuse circuit 80 are held at a logic low level. Since output f of fuse circuit 80 is held at a logic low level, transfer gate 82 of each of address program circuits 70.1-70.m is rendered nonconductive, and outputs REDA1-REDAm of address program circuits 70.1-70.m are put in a floating state; however, since output f of enable circuit 71 is held at a logic low level, outputs of redundancy row decoders SD1'-SDm' are held at a logic low level. Accordingly, even if predecode signals A1-Am take any values, spare word line SWL1 is not selected.
On the other hand, in a case where word line WL1 is connected to some defective memory cell 51, and this word line WL1 is replaced by spare word line SWL1, for example, fuse 90 of fuse circuit 80 of each of address program circuits 70.1, . . . corresponding to predecode signals A1-Am designating the defective word line WL1 is cut off and fuse 90 of enable circuit 71 is also cut off. Both outputs f of enable circuit 71 and fuse circuit 80 whose fuses 90 are cut off attain a logic high level, so that transfer gates 82 of address program circuits 70.1, . . . are rendered conductive. Accordingly, if predecode signals A1-Am designating defective word line WL1 are output from row address predecoder group 63, outputs REDA1, . . . of all address program circuits 70.1, . . . having their fuses 90 cut off attain a logic high level, and an output of redundancy row decoder SD1' attains a logic high level. The other redundancy row decoders SD2'-SDn' carry out the same operation.
There also exists a fuse for inactivating row decoder D11 corresponding to defective word line WL1; however, a description will not be given on this fuse.
A description will now be given on the operation of the SRAM shown in FIGS. 14-17. A description will be given on a reading operation in a case where substitution between word line WL1 and spare word line SWL1 is programmed.
Bit line load circuit 54 precharges bit line pairs BL and /BL to a predetermined potential. Row address predecoder group 63 predecodes an external row address signal RA applied via input buffer 62 so as to output predecode signals A1-Am.
In a case where predecode signals A1-Am designate normal word lines WL2-WLui, row decoders D12-Dui corresponding to those predecode signals A1-Am allow those designated word lines WL2-WLui to attain a logic high level.
Conversely, in a case where predecode signals A1-Am designate some defective word line WL1, redundancy row decoder SD1' allows spare word line SWL1 to attain a logic high level in place of row decoder D11 which allows word line WL1 to attain a logic high level.
If word lines WL2-WLui or spare word line SWL1 is raised to a logic high level, any memory cells 51 or any redundancy memory cells 53 connected to those word lines WL2-WLui or that spare word line SWL1 are activated, so that data of the activated memory cells 51 or redundancy memory cells 53 appear as potential differences on bit line pairs BL and /BL. Input buffer 57, column address predecoder group 58 and column decoder group 59 respond to an external column address signal CA to drive column gate 55 and connect a bit line pair BL and /BL of a column corresponding to external column address signal CA and read/write circuit 56. Read/write circuit 56 amplifies the potential difference of the bit line pair BL and /BL to output the amplified potential difference as a data signal Do. For a writing operation, an opposite case to the above described reading operation may be considered.
FIG. 18 is a partly omitted circuit block diagram showing a major portion of another conventional SRAM. While the foregoing description has been made as to the SRAM including spare word lines SWL for use in substitution for defective word lines WL in FIGS. 14-17, a description will now be made on an SRAM including a spare bit line pair (not shown) for use in substitution for a defective bit line pair BL and /BL. Since an overall structure of the SRAM is similar to that of the SRAM shown in FIG. 14 except the fact that there is a replacement between rows and columns and between word lines and bit line pairs, no description will be made on the overall structure of the SRAM.
With reference to FIG. 18, this SRAM includes bit line pairs BL and /BL and word lines WL intersecting with each other, memory cells 51 each provided at intersections of bit line pairs BL and /BL and word lines WL, a bit line load circuit 111 provided at one end of bit line pairs BL and /BL, and a column selecting gate 112 provided at the other end of bit line pairs BL and /BL.
Bit line load circuit 111 includes N channel MOS transistors 103 and 104 each connected between one end of bit line pair BL and /BL and power supply potential lines 101, and a fuse 107 and a high resistance element 108 connected in series between power supply potential line 101 and a ground potential line 102. A connection node N107 between fuse 107 and high resistance element 108 is connected to respective gates of N channel MOS transistors 103 and 104.
Column selecting gate 112 includes N channel MOS transistors 105 and 106 each connected between the other end of bit line pair BL and /BL and a reading/writing circuit not shown, a fuse 109 having its one end supplied with a column selecting signal COL and the other end connected to a node N109, and a resistor 110 connected to node N109 and ground potential line 102. Node N109 is connected to respective gates of N channel MOS transistors 105 and 106.
When memory cell 51 connected to bit line pair BL and /BL is normal, neither fuse 107 nor 109 is cut off. Because of high resistance elements 108 and 110, node N107 is held at a logic high level, and node N109 attains the same level as that of a column selecting signal COL. Accordingly, N channel MOS transistors 103 and 104 are always rendered conductive, and bit line pair BL and /BL is precharged to a power supply potential Vcc via N channel MOS transistors 103 and 104. Further, if column selecting signal COL attains a logic high level, N channel MOS transistors 105 and 106 are rendered conductive. Conversely, if column selecting signal COL attains a logic low level, those transistors 105 and 106 are rendered nonconductive. Accordingly, bit line pair BL and /BL is connected to the reading/writing circuit not shown only when column selecting signal COL attains a logic high level.
On the other hand, if memory cell 51 connected to bit line pair BL and /BL is defective, fuses 105 and 107 are cut off and nodes N107 and N109 are held at a logic low level. Accordingly, N channel MOS transistors 103-106 are always rendered nonconductive and bit line pair BL and /BL is put in a floating state (a non-selection state).
The above described SRAM also includes a fuse circuit for use in applying a column selecting signal COL corresponding to a defective bit line pair BL and /BL to a column selecting gate corresponding to a spare bit line pair; however, a description will not be given on this fuse circuit.
However, the SRAM shown in FIGS. 14-17 has such a disadvantage that if fuse 90 is not cut off, a current i.sub.A (.mu.A) flows from power supply potential line 101 via fuse 90 and high resistance element 92 to ground potential line 102, resulting in an increase in current consumption in proportion to the number of redundancy row decoders SD1'-SDm' or the number of predecode signals A1-Am.
Further, the SRAM shown in FIG. 18 has such a disadvantage that when neither fuse 107 nor 109 is cut off, currents i.sub.B and i.sub.C flow into high resistance elements 108 and 109, resulting in an increase in consumption current in proportion to the number of bit line pairs BL and /BL or the number of column selecting gates 112 connected to the same column selecting signal COL.